`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn 
// 
// Create Date: 2021/11/20 20:32:02
// Design Name: HW2
// Module Name: BCD_dec_adder2bit
// Project Name: hw2
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: Homework 2 for Fudan PLD & HDL courses
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module BCD_dec_adder2bit(
    input cin,
    input clk,
    input ena,
    input rst_n,
    output wire cout,
    output wire [1:0] D,
    output wire [1:0] C,
    output wire [1:0] B,
    output wire [1:0] A
    );
    wire cout_mid;

BCD_dec_adder1bit inst1_BCD_dec_adder1bit(1'b0,clk,ena,rst_n,cout_mid,D[0],C[0],B[0],A[0]);
BCD_dec_adder1bit inst2_BCD_dec_adder1bit(1'b0,clk,cout_mid,rst_n,cout,D[1],C[1],B[1],A[1]);
endmodule
